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1/16 ? semiconductor msm511666c/cl description the msm511666c/cl is a 65,536-word 16-bit dynamic ram fabricated in oki's silicon-gate cmos technology. the msm511666c/cl achieves high integration, high-speed operation, and low-power consumption because oki manufactures the device in a quadruple-layer polysilicon/single-layer metal cmos process. the msm511666c/cl is available in a 40-pin plastic soj or 44/40-pin plastic tsop. the msm511666cl (the low-power version) is specially designed for lower-power applications. features ? 65,536-word 16-bit configuration ? single 5 v power supply, 10% tolerance ? input : ttl compatible, low input capacitance ? output : ttl compatible, 3-state ? refresh : 256 cycles/4 ms, 256 cycles/32 ms (l-version) ? byte write and fast page mode with edo, read modify write capability ? cas before ras refresh, hidden refresh, ras -only refresh capability ? package options: 40-pin 400 mil plastic soj (soj40-p-400-1.27) (product : msm511666c/cl-xxjs) 44/40-pin 400 mil plastic tsop (tsopii44/40-p-400-0.80-k) (product : msm511666c/cl-xxts-k) xx indicates speed rank. product family ? semiconductor msm511666c/cl 65,536-word 16-bit dynamic ram : fast page mode type with edo (byte write) msm511666c/cl-70 70 ns 120 ns 110 ns 495 mw 550 mw family access time (max.) cycle time (min.) standby (max.) power dissipation msm511666c/cl-60 t rac 60 ns 35 ns t aa 30 ns 20 ns t cac 20 ns 20 ns t oea 20 ns operating (max.) 5.5 mw/ 1.1 mw (l-version) e2g0015-17-41 this version: jan. 1998 previous version: may 1997
2/16 ? semiconductor msm511666c/cl pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 v cc dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 nc v cc uwe lwe ras a0 a1 a2 a3 a4 v cc v ss dq16 dq15 dq14 dq13 dq12 dq11 dq10 dq9 nc v ss cas oe nc nc nc a7 a6 a5 v ss 1 v cc 40-pin plastic soj 44/40-pin plastic tsop (k type) 22 v cc 2 dq1 3 dq2 4 dq3 5 dq4 6 dq5 7 dq6 8 dq7 9 dq8 10 nc 13 v cc 14 uwe 15 lwe 16 ras 17 a0 18 a1 19 a2 20 a3 21 a4 44 v ss 23 v ss 43 dq16 42 dq15 41 dq14 40 dq13 39 dq12 38 dq11 37 dq10 36 dq9 35 nc 32 v ss 31 cas 30 oe 29 nc 28 nc 27 nc 26 a7 25 a6 24 a5 note : the same power supply voltage must be provided to every v cc pin, and the same gnd voltage level must be provided to every v ss pin. pin name function a0 - a7 address input ras row address strobe cas column address strobe dq1 - dq16 data input/data output oe output enable lwe lower byte write enable v cc power supply (5 v) nc no connection uwe upper byte write enable v ss ground (0 v)
3/16 ? semiconductor msm511666c/cl block diagram timing generator ras cas timing generator internal address counter row address buffers a0 - a7 v cc v ss on chip v bb generator row de- coders word drivers memory cells refresh control clock sense amplifiers column decoders write clock generator i/o selector output buffers lwe oe 16 dq1 - dq16 16 16 16 16 16 input buffers 16 8 88 column address buffers 8 uwe function table function mode ras h l input pin cas * h uwe lwe h l h oe l h l l l l l l h h l * * * * * h word read refresh standby lower byte write dq pin dq1 - dq8 high-z high-z d in dq9 - dq16 high-z high-z d out don't care d out don't care d in upper byte write l ll lh d in d in word write h ll hh high-z high-z * *: "h" or "l"
4/16 ? semiconductor msm511666c/cl electrical characteristics absolute maximum ratings recommended operating conditions capacitance *: ta = 25 c voltage on any pin relative to v ss short circuit output current power dissipation operating temperature storage temperature v t symbol i os p d * t opr t stg C1.0 to 7.0 50 1 0 to 70 C55 to 150 rating ma w c c parameter v unit power supply voltage input high voltage input low voltage v cc symbol v ss v ih v il 5.0 0 typ. parameter 4.5 0 2.4 C1.0 min. 5.5 0 6.5 0.8 max. (ta = 0c to 70c) v unit v v v input capacitance (a0 - a7) input capacitance output capacitance (dq1 - dq16) c in1 symbol c in2 c i/o 7 7 7 max. pf unit pf pf parameter (v cc = 5 v 10%, ta = 25c, f = 1 mhz) typ. ( ras , cas , uwe , lwe , oe )
5/16 ? semiconductor msm511666c/cl dc characteristics parameter symbol condition msm511666 c/cl-70 msm511666 c/cl-60 (v cc = 5 v 10%, ta = 0c to 70c) i oh = C2.5 ma output high voltage i ol = 2.1 ma output low voltage 0 v v i 6.5 v; all other pins not input leakage current under test = 0 v dq disable output leakage current 0 v v o 5.5 v ras , cas cycling, average power t rc = min. supply current (operating) ras , cas = v ih power supply ras , cas current (standby) ras cycling, average power cas = v ih , supply current t rc = min. ( ras -only refresh) ras = v ih , power supply cas = v il , current (standby) dq = enable average power cas before ras supply current ( cas before ras refresh) ras = v il , average power cas cycling, supply current t hpc = min. (fast page mode) t rc = 125 m s, average power v oh v ol i li i lo i cc1 i cc2 i cc3 i cc5 i cc6 i cc7 i cc10 cas before ras , supply current t ras 1 m s (battery backup) 3 v cc C0.2 v min. 2.4 0 C10 C10 max. v cc 0.4 10 10 90 2 1 90 5 90 85 300 200 min. 2.4 0 C10 C10 max. v cc 0.4 10 10 100 2 1 100 5 100 95 300 200 unit v v m a m a ma ma ma ma ma ma m a m a note 1, 2 1 1, 2 1 1, 2 1, 3 1, 4, 5 1, 5 ras cycling, notes : 1. i cc max. is specified as i cc for output open condition. 2. the address can be changed once or less while ras = v il . 3. the address can be changed once or less while cas = v ih . 4. v cc C 0.2 v v ih 6.5 v, C1.0 v v il 0.2 v. 5. l-version.
6/16 ? semiconductor msm511666c/cl ac characteristics (1/2) parameter (v cc = 5 v 10%, ta = 0c to 70c) note 1, 2, 3 random read or write cycle time read modify write cycle time fast page mode cycle time fast page mode read modify write cycle time access time from ras access time from cas access time from column address access time from cas precharge ras to data output buffer turn-off delay time transition time ras precharge time ras pulse width ras pulse width (fast page mode with edo) ras hold time cas pulse width cas hold time ras to cas delay time ras to column address delay time cas to ras precharge time row address set-up time row address hold time column address set-up time column address hold time column address hold time from ras column address to ras lead time access time from oe oe to data output buffer turn-off delay time refresh period ras hold time referenced to oe unit ras hold time from cas precharge note output low impedance time from cas cas precharge time (fast page mode with edo) refresh period (l-version) symbol t rc t rwc t hpc t hprwc t rac t cac t aa t cpa t rez t t t rp t ras t rasp t rsh t cas t csh t rcd t rad t crp t asr t rah t asc t cah t ral t oea t oez t ref t roh t rhcp t clz t cp t ar t ref msm511666 c/cl-70 msm511666 c/cl-60 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns 4, 5, 6 4, 5 4, 6 4 7, 8 5 6 4 7 4 3 cas to data output buffer turn-off delay time t cez ns 7, 8 data output hold after cas low t doh ns we to data output buffer turn-off delay time t wez ns 7 oe hold time from cas (dq disable) t cho ns ras to second cas delay time t rscd ns min. 110 155 25 65 0 0 1 40 60 60 20 10 10 50 20 15 5 0 10 0 10 45 30 0 15 0 5 0 5 60 35 max. 60 20 30 35 15 50 10,000 100,000 10,000 40 30 20 15 4 32 15 15 ns min. 120 170 30 70 0 0 1 40 70 70 20 10 10 55 20 15 5 0 10 0 10 55 35 0 15 0 5 0 5 70 40 max. 70 20 35 40 15 50 10,000 100,000 10,000 50 35 20 15 4 32 15 15
7/16 ? semiconductor msm511666c/cl ac characteristics (2/2) write command pulse width write command to cas lead time write command to ras lead time data-in set-up time data-in hold time from ras cas to we delay time ras to we delay time column address to we delay time ras to cas hold time ( cas before ras ) cas active delay time from ras precharge data-in hold time write command hold time write command hold time from ras oe command hold time oe to data-in delay time (v cc = 5 v 10%, ta = 0c to 70c) note 1, 2, 3 write command set-up time parameter ras to cas set-up time ( cas before ras ) cas precharge we delay time msm511666 c/cl-70 msm511666 c/cl-60 read command set-up time read command hold time read command hold time referenced to ras we pulse width (dq disable) oe command hold time oe precharge time symbol t wp t cwl t rwl t ds t dhr t cwd t rwd t awd t chr t rpc t dh t wch t wcr t oeh t oed t wcs t csr t cpwd t rcs t rch t rrh t wpe t och t oep 0 0 0 min. 10 20 20 0 40 40 80 50 5 10 0 10 10 40 10 15 0 55 7 10 10 max. unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns note 11 10 10 10 11 10 10 9 9 0 0 0 min. 10 20 20 0 45 45 95 60 5 10 0 10 10 45 10 15 0 65 7 10 10 max.
8/16 ? semiconductor msm511666c/cl notes: 1. a start-up delay of 100 m s is required after power-up, followed by a minimum of eight initialization cycles ( ras -only refresh or cas before ras refresh) before proper device operation is achieved. 2. the ac characteristics assume t t = 5 ns. 3. v ih (min.) and v il (max.) are reference levels for measuring input timing signals. transition times (t t ) are measured between v ih and v il . 4. this parameter is measured with a load circuit equivalent to 1 ttl load and 50 pf. the output timing reference levels are v oh = 2.0 v (i oh = C2 ma) and v ol = 0.8 v (i ol = 2 ma). 5. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then the access time is controlled by t cac . 6. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then the access time is controlled by t aa . 7. t cez (max.), t rez (max.), t wez (max.) and t oez (max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. t cez and t rez must be satisfied for open circuit condition. 9. t rch or t rrh must be satisfied for a read cycle. 10. t wcs , t cwd , t rwd , t awd and t cpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. if t cwd 3 t cwd (min.) , t rwd 3 t rwd (min.), t awd 3 t awd (min.) and t cpwd 3 t cpwd (min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. these parameters are referenced to the cas leading edge in an early write cycle, and to the we leading edge in an oe control write cycle, or a read modify write cycle.
9/16 ? semiconductor msm511666c/cl timing waveform read cycle write cycle (early write) "h" or "l" ras cas v ih v il C C v ih v il C C dq v oh v ol C C address v ih v il C C we v ih v il C C oe v ih v il C C t rc t ras t rp t ar t crp t csh t crp t rcd t rsh t cas t rad t asr t rah t asc t cah t ral row column t rcs t rrh t rch t aa t roh t oea t cac t rac t oez t cez open t clz valid data-out t rez "h" or "l" ras cas v ih v il C C v ih v il C C dq v ih v il C C address v ih v il C C we v ih v il C C oe v ih v il C C t rc t ras t rp t ar t crp t rcd t csh t rsh t crp t cas t rad t rah t asr t asc t cah row column t wcs t wch t wcr t dhr t ds t dh valid data-in t wp t ral open t rwl t cwl e2g0095-17-41h
10/16 ? semiconductor msm511666c/cl read modify write cycle "h" or "l" ras cas v ih v il C C v ih v il C C dq v i/oh v i/ol C C address v ih v il C C we v ih v il C C oe v ih v il C C t rwc t ras t rp t ar t crp t csh t rcd t crp t rsh t cas t asr t rah t asc t cah row column t cwd t cwl t rwd t rwl t wp t aa t awd t oea t oed t cac t rac t oez t ds t dh t clz valid data-out valid data-in t rad t rcs t oeh
11/16 ? semiconductor msm511666c/cl fast page mode read cycle (part-1) fast page mode read cycle (part-2) C C C C C C C C v ih ras address we dq cas oe C C C C v il v ih v il v ih v il v ih v il v ih v il v oh v ol row column t crp t rp t rasp t cas t csh "h" or "l" column column t rcd t cp t cas t cas t hpc t cah t asc t rad t rcs t aa t rrh t ar t cac t clz t cpa t oea valid data-out valid* data-out t rah t asr t cah t asc t cah t asc t rac valid data-out t aa t cac t doh valid* data-out t cac t rez t oez t oez t cho t och t aa t oea t oep t oep t oea * : same data, t rscd t cp t rhcp e e e e e e e e v ih ras address we dq cas oe C C C C v il v ih v il v ih v il v ih v il v ih v il v oh v ol row column t crp t crp t rp t rasp t cas t csh "h" or "l" column column t rcd t cp t cas t cas t hpc t cp t cah t asc t rad t rcs t rch t rac t aa t ar t cac t clz t wez t oea valid data-out valid data-out valid data-out t rah t asr t cah t asc t cah t asc t cac t aa t doh t cez t cpa t aa t cac t rcs t wpe t rscd t rhcp
12/16 ? semiconductor msm511666c/cl fast page mode write cycle (early write) fast page mode read modify write cycle C C C C C C C C v ih ras address we dq cas oe C C C C v il v ih v il v ih v il v ih v il v ih v il v i/oh v i/ol t asr row column t rasp t cwd t rah column t rcd t cp t asc t cah t cpa t asc t rad t rwd "h" or "l" valid data-out t oez t oed t ds t wp t awd t rcs t cwd t rwl t cac t awd t rac t wp t clz t dh t oeh valid data-in t oea valid data-out t oez t oed t cac t dh t oeh valid data-in t oea t clz t ds t aa t aa t rcs t cah t cpwd t hprwc t crp t ar t cwl t rscd e e e e e e e e v ih ras address we dq cas oe C C C C v il v ih v il v ih v il v ih v il v ih v il v ih v il t asr row column t crp t rp t rasp t cas t csh t rah column column t rcd t cp t cas t cas t hpc t cp t hpc t asc t cah t cah t cah t asc t asc t rad t ar "h" or "l" t dh t ds t wch valid data-in t ds t dh t ds t dh t wch t wch t rsh valid data-in valid data-in t dhr t wcs t wcs t wcs t rscd
13/16 ? semiconductor msm511666c/cl ras -only refresh cycle cas before ras refresh cycle ras cas v ih v il C C v ih v il C C address v ih v il C C t rc t ras t rp t crp t rpc t asr t rah row "h" or "l" dq v oh v ol e e note: we , oe = "h" or "l" t cez open ras cas v ih v il C C v ih v il C C t chr note: we , oe , address = "h" or "l" dq v oh v ol C C t rc t rp t ras t rp t rpc t cp t csr t rpc t cez open
14/16 ? semiconductor msm511666c/cl hidden refresh read cycle hidden refresh write cycle C C C C C C C C v ih ras address we dq cas oe C C C C v il v ih v il v ih v il v ih v il v ih v il v ih v il "h" or "l" t asr row column t crp t rc t asc t rp t ras t rcd t rsh t rad t cah t rah t ral t rwl t chr t ras t rc t rp t ar t dhr t ds t wp t wch t dh valid data-in t wcr t wcs ras cas address oe v ih v il C C v ih v il C C v ih v il C C v ih v il C C "h" or "l" we v ih v il C C dq v oh v ol C C t rc t rc t ras t rp t ras t rp t ar t crp t rcd t rsh t chr t rad t asr t rah t asc t cah row column t rcs t ral t rrh t aa t roh t oea t cac t rac t clz t oez valid data-out open t cez t rez
15/16 ? semiconductor msm511666c/cl (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). soj40-p-400-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.70 typ. mirror finish
16/16 ? semiconductor msm511666c/cl (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.49 typ. tsop ii 44/40-p-400-0.80-k mirror finish

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